In modern communication systems, it is very important to provide a synthesizer with a high-speed prescaler. Usually, high-speed prescalers are integrated into BJT technologies or AsGa technologies. However, with the progress of CMOS technology, which provides higher integration density, lower power consumption and faster operating speed, a prescaler using CMOS technology has been provided.
FIG. 1 (Prior Art) is a circuit diagram of a conventional divide-by-128/129 counter using CMOS technologies. The divide-by-128/129 counter comprises a high-speed divide-by-4/5 counter K1, a low-speed divide-by-32 counter K2, and a control circuit K3. The high-speed divide-by-4/5 counter K1 is a logic circuit derived from the state diagram, in which three D flip-flops D1, D2, D3 and two NAND gates NA1, NA2 are connected as in FIG. 1. A divide-by-4/5 control signal MC is provided to control the input clock divided by 4 or by 5. The low-speed divide-by-32 counter K2 is formed by serially connecting five T flip-flops T1, T2, T3, T4, T5 (a T flip-flop can be obtained by connecting the input terminal (D) and the inverting output terminal (Q') of a D flip-flop), for dividing the inputted clock signal by 32. The control circuit K3 is used to provide the divide-by-4/5 control signal MC for the divide-by-4/5 counter K1 when the inverting output terminals of five T flip-flops T1, T2, T3, T4, T5 of the divide-by-32 counter K2 are all logic 1 and a mode control signal MODE is also 1 (that is, a period of the divide-by-32 counter K2).
In this example, when the mode control signal MODE is 0, the divide-by-4/5 control signal must be 0, at this time, the divide-by-4/5 counter divides the input clock IN by 4. And therefore, the divide-by-128/129 divides the input clock IN by 128 to obtain an output OUT. On the contrary, when the mode control signal is 1, the divide-by-4/5 control signal MC of the divide-by-4/5 counter K1 outputs a 1 every period of the divide-by-32 counter K2, the divide-by-4/5 counter K1 divides the input clock IN by 5 once every period of the divide-by-32 counter K2, therefore, the divide-by-128/129 counter in this case divides the input clock IN by 129.
For high-frequency signals that are transmitted and processed in the divide-by-4/5 counter K1, the operating frequency of the divide-by-128/129 counter is restricted by the divide-by-4/5 counter K1.